1. Field of the Invention
The present invention relates to a method and a circuit system for detecting an error in an A/D converter.
2. Description of the Related Art                So-called converters are used for converting electronic signals, and analog signals are converted into digital signals using analog-digital (A/D) converters. Correspondingly, digital-analog (D/A) converters are used to convert digital signals into analog signals. During operation of such converters, errors may arise which are to be detected in order to increase the operational reliability.        
Various methods are known in the related art for ensuring the reliability of A/D converters. The use of an alternating logic system is proposed in the publication “Test Generation and Concurrent Error Detection in Current-Mode A/D Converters,” IEEE, 1995, by Wey, Chin-Long, Shoba Krishnan, and Sondes Sahli. In this cited document, first a current It1=Iin to be measured is digitized with the aid of an A/D converter and the result is stored in a register, and in the next step a current It2=Iref−Iin is ascertained. The two digital values thus obtained for the currents are then compared to one another. In the error-free case, the second value of current It2 is complementary to the first value of current It1. This method is based on time redundancy; i.e., the clock time of the A/D converter must be equal to or greater than twice the conversion time, so that two conversions can be carried out during a clock period. However, this requirement cannot be met for every application.
In the publication “A Proposal for Error Tolerating Codes,” IEEE, 1993, by Takashi Matsubara and Yoshiaki Koga, the use of error-tolerant codes for A/D converters is proposed. A window comparator is used for each bit, the individual window comparators having different voltage ranges. One of the window comparators supplies a logical “1” when the analog input voltage is in a voltage range covered by this window comparator. The outputs of the window comparators are able to implement an error-tolerant code in this way. However, this publication does not state how errors may be detected, or how much additional hardware (HW overhead) is required for this error detection.